2.3.10

　　Boot modes

　　At startup, boot pins are used to select one of three boot options:

　　<

　　Boot from user Flash: you have an option to boot from any of two memory banks. By

　　default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash

　　memory bank 2 by setting a bit in the option bytes.

　　<

　　Boot from system memory

　　<

　　Boot from embedded SRAM

　　The boot loader is located in system memory. It is used to reprogram the Flash memory by

　　using USART1.

　　2.3.11

　　Power supply schemes

　　<

　　VDD= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

　　Provided externally through VDDpins.

　　<

　　VSSA, VDDA= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,

　　RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC

　　is used). VDDAand VSSAmust be connected to VDDand VSS, respectively.

　　<

　　VBAT= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

　　registers (through power switch) when VDDis not present.

　　For more details on how to connect power pins, refer to Figure 12: Power supply scheme.

　　2.3.12

　　Power supply supervisor

　　The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is

　　always active, and ensures proper operation starting from/down to 2 V. The device remains

　　in reset mode when VDDis below a specified threshold, VPOR/PDR, without the need for an

　　external reset circuit.

　　The device features an embedded programmable voltage detector (PVD) that monitors the

　　VDD/VDDApower supply and compares it to the VPVDthreshold. An interrupt can be

　　generated when VDD/VDDAdrops below the VPVDthreshold and/or when VDD/VDDAis higher

　　than the VPVDthreshold. The interrupt service routine can then generate a warning

　　message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

　　Table 12: Embedded reset and power control block characteristics for the values of

　　VPOR/PDRand VPVD