2.3.6

　　LCD parallel interface

　　The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It

　　supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

　　specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-

　　effective graphic applications using LCD modules with embedded controllers or high-

　　performance solutions using external controllers with dedicated acceleration.

　　2.3.7

　　Nested vectored interrupt controller (NVIC)

　　The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested

　　vectored interrupt controller able to handle up to 60 maskable interrupt channels (not

　　including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

　　<

　　Closely coupled NVIC gives low latency interrupt processing

　　<

　　Interrupt entry vector table address passed directly to the core

　　<

　　Closely coupled NVIC core interface

　　<

　　Allows early processing of interrupts

　　<

　　Processing of late arriving higher priority interrupts

　　<

　　Support for tail-chaining

　　<

　　Processor state automatically saved

　　<

　　Interrupt entry restored on interrupt exit with no instruction overhead

　　This hardware block provides flexible interrupt management features with minimal interrupt

　　latency.

　　2.3.8

　　External interrupt/event controller (EXTI)

　　The external interrupt/event controller consists of 19 edge detector lines used to generate

　　interrupt/event requests. Each line can be independently configured to select the trigger

　　event (rising edge, falling edge, both) and can be masked independently. A pending register

　　maintains the status of the interrupt requests. The EXTI can detect an external line with a

　　pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected

　　to the 16 external interrupt lines