[3]

　　tHD;DATis the data hold time that is measured from the falling edge of SCL; applies to data in transmission

　　and the acknowledge.

　　[4]

　　A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

　　VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

　　[5]

　　Cb= total capacitance of one bus line in pF.

　　[6]

　　The maximum tffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

　　output stage tfis specified at 250 ns. This allows series protection resistors to be connected in between the

　　SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

　　[7]

　　In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

　　are used, designers should allow for this when considering bus timing.

　　[8]

　　The maximum tHD;DATcould be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than

　　the maximum of tVD;DATor tVD;ACKby a transition time (see UM10204). This maximum must only be met if

　　the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the

　　data must be valid by the set-up time before it releases the clock.

　　[9]

　　tSU;DATis the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

　　transmission and the acknowledge.

　　[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement

　　tSU;DAT= 250 ns must then be met. This will automatically be the case if the device does not stretch the

　　LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

　　output the next data bit to the SDA line tr(max)+ tSU;DAT= 1000 + 250 = 1250 ns (according to the

　　Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must

　　meet this set-up time.