8.21.6.4

　　Power-down mode

　　In Power-down mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all

　　clock sources are off except for watchdog oscillator or low-power oscillator if selected. In

　　addition all analog blocks and the flash are shut down. In Power-down mode, the

　　application can keep the watchdog oscillator and the BOD circuit running for self-timed

　　wake-up and BOD protection.

　　The LPC81xM can wake up from Power-down mode via a reset, digital pins selected as

　　inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the

　　USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C

　　blocks (in slave mode).

　　Any interrupt used for waking up from Power-down mode must be enabled in one of the

　　SYSCON wake-up enable registers and the NVIC.

　　Power-down mode reduces power consumption compared to Deep-sleep mode at the

　　expense of longer wake-up times.

　　8.21.6.5

　　Deep power-down mode

　　In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP

　　pin and the self wake-up timer if enabled. Four general-purpose registers are available to

　　store information during Deep power-down mode. The LPC81xM can wake up from Deep

　　power-down mode via the WAKEUP pin, or without an external signal by using the

　　time-out of the self wake-up timer (see Section 8.18).

　　The LPC81xM can be prevented from entering Deep power-down mode by setting a lock

　　bit in the PMU block. Locking out Deep power-down mode enables the application to keep

　　the watchdog timer or the BOD running at all times.

　　When entering Deep power-down mode, an external pull-up resistor is required on the

　　WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in

　　Deep power-down mode.