8.21.6.3

　　Deep-sleep mode

　　In Deep-sleep mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all

　　clock sources are off except for the IRC and watchdog oscillator or low-power oscillator if

　　selected. The IRC output is disabled. In addition all analog blocks are shut down and the

　　flash is in stand-by mode. In Deep-sleep mode, the application can keep the watchdog

　　oscillator and the BOD circuit running for self-timed wake-up and BOD protection.

　　The LPC81xM can wake up from Deep-sleep mode via a reset, digital pins selected as

　　inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the

　　USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C

　　blocks (in slave mode).

　　Any interrupt used for waking up from Deep-sleep mode must be enabled in one of the

　　SYSCON wake-up enable registers and the NVIC.

　　Deep-sleep mode saves power and allows for short wake-up times.

　　8.21.6.4

　　Power-down mode

　　In Power-down mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all

　　clock sources are off except for watchdog oscillator or low-power oscillator if selected. In

　　addition all analog blocks and the flash are shut down. In Power-down mode, the

　　application can keep the watchdog oscillator and the BOD circuit running for self-timed

　　wake-up and BOD protection.

　　The LPC81xM can wake up from Power-down mode via a reset, digital pins selected as

　　inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the

　　USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C

　　blocks (in slave mode).

　　Any interrupt used for waking up from Power-down mode must be enabled in one of the

　　SYSCON wake-up enable registers and the NVIC.

　　Power-down mode reduces power consumption compared to Deep-sleep mode at the

　　expense of longer wake-up times