8.21.4 Clock output

　　The LPC81xM features a clock output function that routes the IRC, the SysOsc, the

　　watchdog oscillator, or the main clock to the CLKOUT function. The CLKOUT function can

　　be connected to any digital pin through the switch matrix.

　　8.21.5 Wake-up process

　　The LPC81xM begin operation at power-up by using the IRC as the clock source. This

　　allows chip operation to resume quickly. If the SysOsc, the external clock source, or the

　　PLL is needed by the application, software must enable these features and wait for them

　　to stabilize before they are used as a clock source.

　　8.21.6 Power control

　　The LPC81xM supports the ARM Cortex-M0 Sleep mode. The CPU clock rate may also

　　be controlled as needed by changing clock sources, reconfiguring PLL values, and/or

　　altering the CPU clock divider value. This allows a trade-off of power versus processing

　　speed based on application requirements. In addition, a register is provided for shutting

　　down the clocks to individual on-chip peripherals, allowing to fine-tune power

　　consumption by eliminating all dynamic power use in any peripherals that are not required

　　for the application. Selected peripherals have their own clock divider which provides even

　　better power control.

　　8.21.6.1

　　Power profiles

　　The power consumption in Active and Sleep modes can be optimized for the application

　　through simple calls to the power profile API. The API is accessible through the on-chip

　　ROM.

　　The power configuration routine configures the LPC81xM for one of the following power

　　modes:

　　•Default mode corresponding to power configuration after reset.

　　•CPU performance mode corresponding to optimized processing capability.

　　•Efficiency mode corresponding to optimized balance of current consumption and CPU

　　performance.

　　•Low-current mode corresponding to lowest power consumption.

　　In addition, the power profile includes routines to select the optimal PLL settings for a

　　given system clock and PLL input clock.

　　8.21.6.2

　　Sleep mode

　　When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

　　mode does not need any special sequence but re-enabling the clock to the ARM core.

　　In Sleep mode, execution of instructions is suspended until either a reset or interrupt

　　occurs. Peripheral functions continue operation during Sleep mode and may generate

　　interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

　　power used by the processor itself, memory systems and related controllers, and internal

　　buses.