8.21.1.3

　　Internal Low-power Oscillator and Watchdog Oscillator (WDOsc)

　　The nominal frequency of the WDOsc is programmable between 9.4 kHz and 2.3 MHz.

　　The frequency spread over silicon process variations is

　　 40%.

　　The WDOsc is a dedicated oscillator for the windowed WWDT.

　　The internal low-power 10 kHz (

　　 40% accuracy) oscillator serves a the clock input to the

　　WKT. This oscillator can be configured to run in all low power modes.

　　8.21.2 Clock input

　　A 3.3 V external clock source (25 MHz typical) can be supplied on the selected CLKIN pin

　　or a 1.8 V external clock source can be supplied on the XTALIN pin (see Section 14.1).

　　8.21.3 System PLL

　　The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

　　frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

　　The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

　　156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

　　its frequency range while the PLL is providing the desired output frequency. The output

　　divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the

　　minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.

　　The PLL is turned off and bypassed following a chip reset and may be enabled by

　　software. The program must configure and activate the PLL, wait for the PLL to lock, and

　　then connect to the PLL as a clock source. The PLL settling time is nominally 100